Conventionally, a row access in DRAM (dynamic random access memory) turns on the transistors of all the memory cells that belong to a selected row address. In a DRAM, data stored in a memory cell as an electric charge. When the transistor of a particular memory cell is turned on, the electric charge in the memory cell and the electric charge on the bitline attached thereto will be shared. This charge sharing corrupts the data stored as the electric charge in the memory cell. At completion of the row access in DRAMs, the DRAM must activate a sense amplifier on each pair of bitlines to restore the data stored in memory cells belonging to the accessed row address. Therefore, in conventional DRAMs, a sense amplifier is needed for each pair of bitlines, and every sense amplifier must be activated on every row access.
In page mode, which is one of the DRAM access methods, data held in activated sense amplifiers are accessed, thereby enabling a very fast access. A burst mode, which is a more advanced fast access mode used in SDRAM (synchronous DRAM) and some Rambus architectures, also relies on the same page mode. It realizes a faster cycle time in column access by generating column addresses internally within a memory chip. However, fast access mode such as the page mode is limited to a method that accesses different column addresses on a selected wordline.
Certain features of DRAMs will now be described as background to the invention, but are not admitted to be prior art. FIG. 3A shows a basic operation of DRAM. When the row address is changed, the DRAM must perform a sequence of operations: (i) restore all data on the wordline that has been selected, (ii) precharge bitlines, (iii) activate a new wordline, (iv) wait until a read signal is provided onto a bitline pair, and (v) start the operation of a sense amplifier, thus resulting in a very long access time and cycle time.
As shown in FIG. 3B, access mode of typical SDRAM DDR (synchronous DRAM Double Data Rate) enables (a) a fast column access in burst mode. However, (b) cycle time between row addresses (Row-to-Row Cycle time) is long because the Array Time Constant, which is the time interval from when the wordline is activated to completing the precharge of a bitline, is large. Its burst data rate is high, but its net data rate averaged over a number of random row accesses is very low. The net data rate is only 4/12=33% of the peak data rate because data bursts are performed at 4 clock edges out of 12 clock edges. To improve this random row access, DRAM has a plurality of banks.
For practical design reasons, the number of banks is typically limited to only two to four per memory chip and the use of fast random row accesses is also considerably limited. Thus, in typical DRAM, column accesses (horizontal accesses) are fast, but row accesses (vertical accesses) are very slow.
In a conventional memory such as SRAM (Static RAM) and DRAM, which stores data as an electric charge, every memory array consists of a matrix of a plurality of wordlines and bitlines. A new access cannot be performed as long as one of the wordlines or bitlines is active. Theoretically, memory cycle time is therefore defined by an array time constant, which is a time interval from the activation of the wordline to the completion of precharge of the bitline, as shown in FIG. 3A.
A read operation and a write operation in typical SRAM and DRAM are both performed by activating the same node (through a selected wordline and a selected bitline). Because data is stored as an electric charge, a read operation can accidentally write data or corrupt the stored data if there is overlap of timing signals. For example, if a new wordline starts activating before the previous wordline has been turned off, all data coupled to the two wordlines collide with each other through a common bitline pair. Bit switch overlap can also cause the corruption of data stored with an electric charge shared between memory cells coupled to two bitlines through a data line. In order to provide sufficient design margin, the array time constant must be increased to allow enough time for satisfying the timing constraints. Consequently, cycle time becomes much longer than a theoretical array time constant, thus resulting in a low memory operation speed.
It is an object of the present invention to provide a memory circuit block and a method for accessing the memory circuit block that allow fast operation.